When high-speed and low voltage swing data transfer is needed, differential signaling (also commonly referred to as double ended signaling) is perhaps the most robust and promising signaling concept. Differential signaling can add an additional measure of noise immunity due to the fact that the transmitted signal is carried on two conductors and is the difference of the two signals on the two conductors. Current mode logic (CML), a design technique commonly used in high speed signaling applications such as high-speed data communication systems, communications chips and routers, uses differential signaling.
Current-mode-logic (CML) circuits have been widely used in high-speed data communication systems due largely in part to improved switching speeds when compared with voltage-mode-logic circuits. CML circuits can operate with low signal voltage and higher operating frequency at lower supply voltage than static CMOS circuits. CML is also widely used in high-speed applications due to its relatively low power consumption and low supply voltage when compared to other types of logic designs, such as emitter coupled logic (ECL). CML is also considerably faster than CMOS due to its lower voltage swings.
CML has an additional advantage over other high-speed forms of logic such as logic using Gallium Arsenide (GaAs) in that CML can be fabricated using the same fabrication lines as the widely used CMOS circuits, thus allowing CML circuits to be created on high-technology fabrication lines without requiring a significant outlay of money to create a special fabrication line. Additionally, CML logic may cohabitate with CMOS logic on the same integrated circuit. Therefore, such hybrid circuits can combine the high-speed aspects of CML logic and the low power requirements of CMOS logic.
As those in the art will understand, the standard MOS CML structure, whether MUX circuit, AND2 gate, data latch, etc., comprises three main parts: the pull up resistors, the pull down network switch and the current source. The inputs to the pull down network are fully differential. The pull down network can implement any logic function (MUX, AND, OR, XOR, etc.) but must have a definite value for all possible input combinations. The pull down network is regulated by a constant current source referred to as the tail current source. The pull down network steers the current from the current source to one of the pull up resistors based upon the implemented logic function. The resistor connected to the current source through the pull down network will have current flowing therethrough, causing a voltage drop, whereas the other resistor will not have any current flowing through its output node and will be pulled up to VDD. The output swing is set exclusively by the amount of current and the value of the resistor load and is generally much smaller than VDD, in the order of a few hundred millivolts.
FIG. 1 is a circuit diagram of a prior art CML data latch 10, more specifically a falling edge triggered CML D flip-flop. The operation and structure of the data latch 10, as well as modification thereto, should be familiar to those in the art, but are briefly described hereafter. The CML data latch 10 includes a pair of differential outputs OUTP and OUTN coupled to load resistors R1 and R2; a tail current source 12 which may comprises a NMOS transistor; an input tracking stage including transistors M3 and M4, utilized to sense and track the data variation, e.g., the data signals data not (DN) and data (D); and a cross-coupled regenerative pair, transistors M5 and M6, for providing positive feedback to store the data. The track and latch modes are determined by the clock signal input to a second differential pair, transistors M1 and M2.
When signal clock not (CLKB) is high, selection transistor M1 is on, coupling tail current source 12 to the track transistors M3, M4. Selection transistor M2, coupled to latch transistors M5 and M6, receives low signal CLK and is off, disconnecting transistors M5 and M6 from current source 12. Transistors M5 and M6 are off. In this state, the track transistors M3, M4 essentially sense and transfer the data to the outputs OUTP and OUTN. If D is high, meaning DN is low, M4 is on and M3 is off. Node OUTP goes to VDD, as no current flows through resistor R1. Node OUTN goes to a lower voltage (VDD−R2*it), as the tail current flows through transistor M4 and R2.
When CLK is high, M1 is off, the tracking mode is disabled meaning that the tracking transistors M3 and M4 are disconnected from current source 12. Selection transistor M2 is on enabling the tail current it to flow through the regenerative pair consisting of transistors M5 and M6 which stores the logic state at the OUTP and OUTN nodes. Whatever data at nodes OUTN and OUTP at this transition time are latched. The outputs stay at this data state until the next clock transition, thereby isolating the output from the input.
In deep submicron CMOS technologies, such as 0.13 μm technology and below, the typical power supply is 1.0V. Often, a power supply has +5% to −10% tolerance variations. Therefore, with a 1.0V VDD, the worst case power supply can be 0.9V. In the circuit of FIG. 1, the output swing is set exclusively by the amount of tail current (it) and the value of the resistor load (R1, R2) and is generally much smaller than VDD, in the order of a few hundred millivolts. In most data communication applications, a single-ended-peak output swing of 0.2V (e.g., R*it/2) is often required. With a single-ended-peak output swing of 0.2V, the output common mode voltage of the latch circuit is 0.7V (e.g., VDD−0.2V). The CML latch circuit 10 suffers from severe headroom problems when designed in a 1.0V (worst case 0.9V) supply voltage. When CLKB is high, the common-mode voltage at the inputs (e.g., D and DN) needs to ensure that transistors M3, M4, M1 and the tail current transistor are operated in saturation mode. Similarly, when CLK is high, the common-mode voltage at the outputs (e.g., OUTP and OUTN) needs to drive transistors M5, M6, M2 and the tail current transistor into saturation mode. Therefore, the common-mode voltage at both the inputs and the outputs need to satisfy the following equation:VCM≧VTH-NMOS+2VDSAT-NMOS.  (1)In EQ. (1), VTH-NMOS is the threshold voltage of the NMOS transistor and is typically about 0.4 to 0.5V in a deep submicron technology; and VDSAT-NMOS is the saturation drain-to-source voltage of the NMOS transistor and is typically around 0.2V. As a result, a VCM larger than at least 0.8V (0.4V+2*0.2V) is required to operate the latch circuit properly. With a worst case VDD of 0.9V and a single-ended-peak output swing of 0.2V (and therefore an output common-mode voltage of 0.7V), the output common-mode voltage is insufficient to drive the transistors into saturation mode. The input nodes (e.g., D and DN) of the latch circuit is often connected to the output nodes of a previous stage CML circuit and therefore the input common-mode is set by the output common-mode voltage of the previous CML circuit. Therefore, it is also difficult to set the input common-mode voltage to be above 0.8V. The design therefore suffers severe headroom problems. The latch circuit cannot acquire a wide input common-mode range, and the output swing of the latch circuit is small reducing the robustness of the circuit. In addition, with the devices in the triode region, the power supply rejection (i.e., rejection of noise from the power supply) is poor resulting in noisy output waveforms.
Addressing these problems in deep submicron CMOS technology is particularly difficult because the threshold voltage VTH-NMOS and the saturation drain-to-source voltage VDSAT-NMOS do not shrink proportionately with reductions in the power supply. Removing the tail current source 12 is one possible method of addressing the headroom issue, thus relying on M1 and M2 to provide the tail current. With this proposed solution, however, the tail current would be inaccurate due to at least the uncertainty of the common-mode voltage and the voltage swing of the CLK and CLKB signals, etc., which results in an inaccurate output common-mode voltage as well as output swing. Also, with an inaccurate tail current, the transconductance of the track stage transistors M3, M4 can vary significantly, requiring oversized transistors M3, M4 for proper tracking operation. Another possible solution to address the headroom issue is to use low threshold voltage transistors. However, this requires extra mask steps in the manufacturing process that are not available in a typical CMOS process. The extra mask steps to lower the threshold voltage also make the manufacturing costs prohibitively expensive.
Therefore, there remains a need for CML circuits, particularly deep submicron CML circuits, with better headroom performance.